1. Field of the Invention
The invention generally relates to semiconductor memory devices and, more particularly, to a method and system for overerase protection of memory cells for nonvolatile memory.
2. Description of the Related Art
Memory devices for nonvolatile storage of information are commonly available in the art. Exemplary nonvolatile semiconductor memory devices include read only memory (ROM), flash memory, programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and electrically erased. Flash EEPROMs further include the additional capability of erasing all memory cells therein at once. The common use of EEPROM semiconductor memory has prompted the development of an EEPROM memory cell with optimal performance characteristics, e.g., shorter programming times, lower voltage usage for programming and reading, longer data retention time, shorter erase time, smaller and miniaturized physical dimensions.
Non-volatile memory devices have been developed by the semiconductor integrated circuit industry for various applications such as computers and digital communications. A variety of non-volatile memory devices with oxide-nitride-oxide (ONO) structures have been developed. An example of a typical non-volatile memory with an ONO structure includes a semiconductor substrate with source and drain regions, and a oxide-nitride-oxide film on top of the substrate surface between the source and the drain. The nitride layer of the ONO film is capable of trapping electrons which are generated in the channel region of the semiconductor substrate during a programming operation.
In programming the memory cell, the respective nitride layer is charged with electrons, causing the turn-on threshold of the memory cell to accordingly increase. As the memory cell is being programmed, it will not turn on and remains nonconductive when being addressed with a read potential applied to its control gate. In erasing the memory cell, holes are injected into the nitride layer to recombine or compensate the stored electrons to accordingly lower the threshold. With the lower threshold, the memory cell accordingly turns on and changes into a conductive state when being addressed with a read potential to the control gate.
For a localized trapping storage nonvolatile memory, the memory programming is performed by hot electron injection at the channel, whereas memory erase is performed by band-to-band hot hole injection. FIG. 1 is a schematic view that illustrates an exemplary erase operation for a flash memory cell according to a method in the art using hot hole injection. In each erase shot, a positive voltage is applied to the drain 101, the gate 102 is negatively biased, the source 100 is floated and the substrate is grounded. According to this particular example of an erase operation in the art, the voltage of the gate is −4 volts (V) in each erase shot where the drain voltage is 6V for each shot. As a positive voltage is applied to the drain 101, an electric field is formed along a path from the drain 101 to the gate 102. The holes flowing out of the drain 101 are accordingly directed to the gate 102 and are then trapped in the trapping layer in completing the erase operation. An erase verify step is performed after each erase shot to verify the completeness of the erase operation.
FIG. 2 is a schematic view that further illustrates another exemplary memory erase operation in the art using band-to-band hot hole injection. In contrast to the exemplary memory erase operation described in conjunction with FIG. 1, the positive voltage applied in the drain 101 is raised as the erase shot increases, as the gate 102 is biased, the source 100 is floated and the substrate 106 is grounded for each erase shot. The holes at the drain 101 include raising voltage potentials. Using a raising voltages can increase amount of hot holes pumped into the trapping layer and increase erase strength as the shot number increases and the erase time can be largely reduced. The speed of the memory erase operation is affected by the length of the channel. The erase speed of a relatively short channel is much higher than that of a long channel, which results in the overerase of the short channel cell. FIG. 3 is a graphical schematic view illustrating an exemplary relationship between the voltage threshold and the program state for the memory erase operation shown in FIG. 2. A large erase speed variation is obtained according to this erase operation algorithm, which will result in overerase in fast erase cells.
For programming a memory array of memory cells according to a method in the art, the respective nitride layer of the addressed cells is injected with electrons, causing a negative charge to accordingly accumulate in the floating gates and the turn-on threshold of the memory cell to increase. As similarly described herein and above, the addressed cells will not turn on as they are being programmed and will accordingly remain nonconductive when addressed with read potentials applied to the respective control gates. In erasing a memory cell having a negatively charged nitride layer, holes are injected into the nitride layer to recombine or compensate the stored electrons to accordingly lower the threshold. With the lower threshold, the memory cell turns on and accordingly changes to a conductive state when addressed with a read potential to the control gate.
As the memory erase requires the lowering of the threshold by accordingly injecting the hot holes to recombine or compensate the stored electrons in the respective nitride layer, memory cells adversely encounter risks of overerase. Overerase occurs if too many holes are injected into the respective nitride layer, which leaves a slightly positive charge therein. This positive charge biases the memory cell and slightly turns it on. As a result, small amounts of current may leak through the memory cell even though it is not addressed at the time of the current leak. A number of overerased memory cells along a given data line can adversely cause an accumulation of leakage current leading to a false reading of data.
In addition to causing false data reading, it is difficult to successfully reprogram overerased memory cells using hot electron programming, particularly if there are embedded algorithms in the integrated circuits. This difficulty arises since the amount of electrons needed to move an overerased memory cell to a programmed state is generally higher than that of memory cells unencumbered by memory overerase. Furthermore, because the memory erase and programming operations impact a plurality of memory cells in a memory array with varying degrees, it is difficult to verify the success of the memory erase and programming operations for the memory array as a whole. In any event, the repair and repair verification processes are often resource-intensive and time-consuming.
Therefore, there is a general need in the art for a nonvolatile memory and corresponding method having an optimal memory erase function and, more particularly, a nonvolatile memory and corresponding method advantageously overcoming at least the aforementioned shortcomings in the art. Moreover, a method and device are needed in the art that optimally correct and repair overerased nonvolatile memory (such as flash, floating gate and ONO film storage nonvolatile memory) in an expeditious and efficient manner.